Parametric decimal division using hardware description language

Jorge Hernan Lopez Botero; Johans Restrepo Cardenas; Jorge Enrique Tóbon Gómez

doi:10.24050/reia.v17i33.1318

Parametric decimal division using hardware description language

10.24050/reia.v17i33.1318

Published 2020-04-06

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Parametric decimal division using hardware description language (J. H. Lopez Botero, J. Restrepo Cardenas, & J. E. Tóbon Gómez, Trans.). (2020). Revista EIA, 17(33), 33016 pp. 1-6. https://doi.org/10.24050/reia.v17i33.1318

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Abstract

In this work we describe a fast and high-precision algorithm written in VHDL Hardware Description Language to perform the division between two_nite decimal numbers, i.e. numbers composed of an integer part and a decimal one, under the scheme of a fixed point representation. The algorithm proposed is not an approximation one as it is usually considered. To do so, the size of the bits of the operands can be tunned by means of a couple of parameters N and M, according to which the latency of the calculation will depend. The project is _nally sinthesized in a _eld programmable gate array or FPGA of the type SPARTAN 3E from XILINX.

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Authors

Jorge Hernan Lopez Botero

Universidad de Antioquia

http://orcid.org/0000-0003-3034-830X (unauthenticated)
Johans Restrepo Cardenas
Jorge Enrique Tóbon Gómez

References

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Parametric decimal division using hardware description language